Process Variation Tolerant 3T1D-Based Cache Architectures
By Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks. Micro, 2007
323 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/118ab6a62342afb3ec237f760f0457a2b41f2c52
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Onur Mutlu
- Mahmut Taylan Kandemir
- Anand Sivasubramaniam
- Emre Kultursay
- Mircea R. Stan
- Jeremie S. Kim
- Yoongu Kim
- Saugata Ghose
In Electrical and Electronic Engineering
In Hardware and Architecture
- Onur Mutlu
- Mahmut Taylan Kandemir
- Anand Sivasubramaniam
- Emre Kultursay
- Mircea R. Stan
- Yoongu Kim
- Jeremie S. Kim
- Saugata Ghose
Citations in the corpus
- Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Researchers have tried to reduce refresh energy in DRAM [19], [34], [36], [37], [58].”
- Relaxing non-volatility for fast and energy-efficient STT-RAM caches (2011, background): “, in the context of 3T-1D memory arrays [13].”