An Implementation of DES and AES, Secure against Some Attacks
By Mehdi-Laurent Akkar, Christophe Giraud. Workshop on Cryptographic Hardware and Embedded Systems, 2001
599 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition
View Paper: https://www.semanticscholar.org/paper/7d91315ccb391bfc1a741b4be6d7638553d9b1e0
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In Artificial Intelligence
- Emmanuel Prouff
- Svetla Nikova
- Vincent Rijmen
- Matthieu Rivain
- Stefan Mangard
- Martin Schläffer
- Norbert Pramstaller
- Elisabeth Oswald
In Computer Vision and Pattern Recognition
- Vincent Rijmen
- Stefan Mangard
- Svetla Nikova
- Emmanuel Prouff
- Matthieu Rivain
- Martin Schläffer
- Christian Rechberger
- Berndt M. Gammel
Citations in the corpus
- Side-Channel Leakage of Masked CMOS Gates (2005, background): “An implementation of an AES co-processor that is based on masking at the gate level has been presented by Trichina and Korkishko in [22, 23].”
- Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard (2003, methodology): “AES is intended to replace the widely used DES and Triple-DES crypto-systems due to the last two’s limited level of security [4], [ 6 ].”
- Multiplicative Masking and Power Analysis of AES (2002, methodology): “In [2], a masking technique is proposed which combines the usual binary additive masking with the multiplicative masking of data, using the multiplication in GF(256), thus avoiding the costly recomputation of the S-boxes.”
- Threshold Implementations Against Side-Channel Attacks and Glitches (2006, background): “This can be done both at the algorithm level [2, 5, 10, 18] and at the gate level [12, 25].”
- Provably Secure Higher-Order Masking of AES (2010, background): “, (sd)l,j) for every rowcoordinate l ∈ [1, 4] and for every column-coordinate j ∈ [1, 4].”
- Successfully Attacking Masked AES Hardware Implementations (2005, methodology): “CMOS implementations of the masking schemes proposed in [12] and [2] leak side-channel information due to glitches.”
- Fault Based Cryptanalysis of the Advanced Encryption Standard (AES) (2003, unknown): “Likewise, the security of AES against side-channel attacks like timing analysis and power analysis, has also been examined, cf. [ AG ,BS99,CJRR,DR1,KQ,KWMK,Me,YT].”
- Statistical Analysis of Second Order Differential Power Analysis (2009, methodology): “Therefore, first order masking (together with hardware countermeasures) is widely used to protect block ciphers implementations against DPA [6], [9], [10].”
- Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, background): “This can be done at the algorithm level [1,5,13,25], at the gate level [15,38] or even in combination with circuit design approaches [27].”
- A Side-Channel Analysis Resistant Description of the AES S-Box (2005, background): “All other operations are linear and can be masked in a straightforward manner as it is for example shown in [2].”