A Side-Channel Analysis Resistant Description of the AES S-Box

By Elisabeth Oswald, Stefan Mangard, Norbert Pramstaller, Vincent Rijmen. Fast Software Encryption Workshop, 2005

353 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Information Systems

View Paper: https://www.semanticscholar.org/paper/7a3341bbf2d40ce82fa5453241473545e36afe80

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Citations in the corpus

Efficient Cache Attacks on AES, and Countermeasures (2010, methodology): “For AES, several masking techniques have been proposed (see, e.g., [ 46 ,53], and the references therein).”
Masking against Side-Channel Attacks: A Formal Security Proof (2013, background): “Further schemes were subsequently published in which masking is applied at hardware or software level at the cost of different area-time-memory trade-offs (see for instance [2,28,30]).”
Threshold Implementations Against Side-Channel Attacks and Glitches (2006, background): “Furthermore, remasking can be effective only if the delays of all the circuits are fully controlled and if there are no glitches [15, 16, 18].”
Pushing the Limits: A Very Compact and a Threshold Implementation of AES (2011, background): “Amongst the countermeasures proposed at different levels of design and abstraction Masking methods, which rely on randomizing key-dependent intermediate values processed during the execution of the cipher, are widely applied on either the algorithmic level [26] or the cell level [27].”
Successfully Attacking Masked AES Hardware Implementations (2005, methodology): “During the last years, several alternative masking schemes have been proposed (see [3], [6], [12], [16], and [17]).”
Provably Secure Higher-Order Masking of AES (2010, methodology): “Tower Field in F4 [28, 29] 77× 10(3) 42 3195 Our scheme for d = 1 This paper 129× 10(3) 73 3153”
Introduction to differential power analysis (2011, background): “be adapted to work with masked inputs and outputs [75–77].”
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, background): “This can be done at the algorithm level [1,5,13,25], at the gate level [15,38] or even in combination with circuit design approaches [27].”
Cache Attacks and Countermeasures: The Case of AES (2006, methodology): “For AES, several masking techniques have been proposed (see e.g. [ 11 ] and the references within).”