Successfully Attacking Masked AES Hardware Implementations

By Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald. Workshop on Cryptographic Hardware and Embedded Systems, 2005

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Provably Secure Higher-Order Masking of AES (2010, background): “Secondly, masking at the hardware level is sensitive to glitches, which induces first-order flaws although in theory every internal wire carries values that are independent of the sensitive variables [20,21].”
Pushing the Limits: A Very Compact and a Threshold Implementation of AES (2011, background): “As expected and also observed in [20], CPA attacks which use a HW model predicting the S-box input or output are not able to recover the secrets of hardware implementations.”
Threshold Implementations Against Side-Channel Attacks and Glitches (2006, background): “Such an implementation of a linear transformation doesn’t leak information that can be used in a side-channel attack, even if presence of glitches is taken into account [15, 16].”
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, background): “Due to these glitches, these circuits are vulnerable to DPA attacks [19, 20].”
On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoqCode Hopping Scheme (2008, background): “The targets considered in the literature are often home-made or known implementations on platforms that are wellknown to the attacker, and are typically examined in an ideal environment [16, 9, 14], for example with an artificially generated trigger signal.”