Multiplicative Masking and Power Analysis of AES

By Jovan Dj. Golic, Christophe Tymen. Workshop on Cryptographic Hardware and Embedded Systems, 2002

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Side-Channel Leakage of Masked CMOS Gates (2005, background): “An implementation of an AES co-processor that is based on masking at the gate level has been presented by Trichina and Korkishko in [22, 23].”
Successfully Attacking Masked AES Hardware Implementations (2005, background): “During the last years, several alternative masking schemes have been proposed (see [3], [6], [12], [16], and [17]).”
Correlation Power Analysis with a Leakage Model (2004, background): “– The data can also be ciphered dynamically during a process by hardware (such as bus encryption) or software means (data masking with a random [11, 7, 20, 10]), so that the handled variables become unpredictable: then no correlation can be expected anymore.”
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, background): “This can be done at the algorithm level [1,5,13,25], at the gate level [15,38] or even in combination with circuit design approaches [27].”
Mutual Information Analysis (2008, background): “Both theory and practice have been developed and as a consequence several more advanced power analysis attacks such as correlation [2], template [3], and higher-order attacks [11] have been proposed as well as a broad range of countermeasures [4, 6 ,7,10].”