Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction

By Rakesh Kumar, Keith I. Farkas, N. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen. Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36., 2003

886 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/f0192fdb1a5e23b32257b4333dc529c40348630a

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Ricardo Bianchini
2. Sunpyo Hong
3. Hyesoon Kim
4. Josep Torrellas
5. Radu Teodorescu
6. Parthasarathy Ranganathan
7. Margaret Martonosi
8. Canturk Isci

In Electrical and Electronic Engineering

1. Ricardo Bianchini
2. Canturk Isci
3. Parthasarathy Ranganathan
4. Pradip Bose
5. Josep Torrellas
6. Margaret Martonosi
7. N. Jouppi
8. Dean M. Tullsen

In Hardware and Architecture

1. Canturk Isci
2. Ricardo Bianchini
3. Parthasarathy Ranganathan
4. Sunpyo Hong
5. Hyesoon Kim
6. Alper Buyuktosunoglu
7. Margaret Martonosi
8. Josep Torrellas

Citations in the corpus

• Qilin: Exploiting parallelism on heterogeneous multiprocessors with adaptive mapping (2009, background): “the Cell and CPU+GPU and single-ISA multiprocessors [ 13 ] such as the upcoming Intel’s Larrabee [32].”
• Single-ISA heterogeneous multi-core architectures for multithreaded workload performance (2004, methodology): “Applications (or different phases of a single application) place different demands on different architectures, stemming from the nature of the computation [14].”
• Easy over hard: a case study on deep learning (2017, neutral): “com/WeiFoo/EasyOverHard CPU clock frequencies [38].”
• An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (2006, background): “[19, 21] propose heterogeneous CMPs in terms of different core complexities.”
• Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, methodology): “[18] propose a CMP with different-complexity cores and the same ISA.”
• Splitwise: Efficient Generative LLM Inference Using Phase Splitting (2023, background): “Research on heterogeneous multiprocessor CPU scheduling attempts to match workload heterogeneity to hardware heterogeneity [29], [40], [41], [50], [76], [80].”
• Energy conservation in heterogeneous server clusters (2005, background): “[18] considered conserving chip-multiprocessor energy by relying on heterogeneous cores.”
• The impact of performance asymmetry in emerging multicore architectures (2005, neutral): “Researchers have proposed numerous such asymmetric processor organizations for power and performance effi-formance efficiency, and have investigated the behavior of multi-programmed single threaded applications on them [5, 8, 9, 11, 17].”
• Core fusion: accommodating software diversity in chip multiprocessors (2007, background): “Asymmetric chip multiprocessors (ACMPs) [3, 23, 24] comprise cores of varying sizes and computational capabilities.”
• Amdahl's Law in the Multicore Era (2008, background): “An alternative to a symmetric multicore chip is an asymmetric (or heterogeneous) multicore chip where one or more cores are more powerful than the others [3, 8, 9, 10, 14].”