Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM

By D. Heidel, Paul W. Marshall, K. Label, J. Schwank, K. Rodbell, M. Hakey, M. Berg, Paul E. Dodd, M. Friendlich, Anthony D. Phan and 3 more. IEEE Transactions on Nuclear Science, 2008

160 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/7a52aedab9b9f83ae138da97653064e24f37b926

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. D. Fleetwood
2. M. Shaneyfelt
3. J. Schwank
4. Paul E. Dodd
5. J. Felix
6. Robert C. Baumann
7. Lloyd W. Massengill
8. Michael Nicolaidis

In Hardware and Architecture

1. Robert C. Baumann
2. J. Felix
3. Paul E. Dodd
4. M. Shaneyfelt
5. J. Schwank
6. Michael Nicolaidis

Citations in the corpus

• Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions (2009, methodology): “Evidence of direct ionization from protons has been reported for 65 nm CMOS technologies [1], [2].”
• Current and Future Challenges in Radiation Effects on CMOS Electronics (2010, background): “Recent experiments on 65-nm and 45-nm SRAMs have shown strong evidence of SEU sensitivity to direct ionization by low-energy protons [48], [49].”
• Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors (2013, result): “These trends are in agreement with previous works [106] and with recent studies [107], [108].”