New unipolar switching power device figures of merit
By A. Huang. IEEE Electron Device Letters, 2004
245 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Mechanical Engineering
View Paper: https://www.semanticscholar.org/paper/76f61fab13e06920c97f1b6f4e94365cd5041f92
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Electrical and Electronic Engineering
- Srabanti Chowdhury
- Umesh K. Mishra
- B. Swenson
- Man Hoi Wong
- D. Moran
- David A. MacDonald
- Isha Maini
- Alex Q. Huang
In Mechanical Engineering
- B. Swenson
- D. Moran
- Srabanti Chowdhury
- David A. MacDonald
- Isha Maini
- Alex Q. Huang
- Man Hoi Wong
- Umesh K. Mishra
Citations in the corpus
- Power Semiconductor Devices for Smart Grid and Renewable Energy Systems (2017, methodology): “Several material figure of merits (FOMs) have been derived by Huang [63] and are updated in Table 1 with recent material data [40], [89]–[90] for a number of important WBG materials with the higher FOMs being better.”
- Surface transfer doping of diamond: A review (2021, background): “Comparison of figures-of-merit for diamond compared with other semiconductors based on Baliga’s and Huang’s analysis [7,18,20].”
- Thermal management and packaging of wide and ultra-wide bandgap power devices: a review and perspective (2023, background): “For a unipolar transistor, the total power loss (Ploss) is the sum of conduction loss (Pcon) and switching loss (Psw), which can be described by [29]”
- Opportunities and Challenges in Very High Frequency Power Conversion (2009, unknown): “and overlap loss during switching [57].”
- CAVET on Bulk GaN Substrates Achieved With MBE-Regrown AlGaN/GaN Layers to Suppress Dispersion (2012, background): “From the figure-of-merit consideration [1], [2], the material system looks attractive for high-power”
- Recent advances in diamond power semiconductor devices (2018, background): “temperature operation capability, and the reduction in chip area [4].”