PuDianNao: A Polyvalent Machine Learning Accelerator

By Dao-Fu Liu, Tianshi Chen, Shaoli Liu, Jinhong Zhou, Shengyuan Zhou, Olivier Temam, Xiaobing Feng, Xuehai Zhou, Yunji Chen. 2015

314 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

1. Ahmad Shawahna
2. Hardik Sharma
3. Michael Ferdman
4. Song Han
5. Aayush Ankit
6. Kaushik Roy
7. Patrick Judd
8. Ji Lin

Citations in the corpus

• PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, unknown): “The DianNao series [17], [18], [46] are good examples of ASICbased NN accelerators; furthermore, the first instruction set architecture for NN accelerators has been proposed, called DianNaoYu [47].”
• ShiDianNao: Shifting vision processing closer to the sensor (2015, unknown): “Recent members of the DianNao family [4, 40] have been optimized for large-scale neural networks and classic machine learning techniques respectively.”
• Stripes: Bit-serial deep neural network computing (2016, methodology): “The rest of the paper is organized as follows: Section II corroborates the per-layer precision requirement variability of DNNs motivating STR, Section III explains the key idea behind STR using a simplified example, Section IV reviews NiN 8-8-8-9-7-8-8-9-9-8-8-8 1.91 8-8-7-9-7-8-8-9-9-8-7-8 1.93 Goo”
• Survey of Machine Learning Accelerators (2020, methodology): “many-tile version of the DianNao for larger NN model inference. The ShiDianNao hShiDianNaoi [41] is designed specifically for convolutional neural network inference. Finally, the PuDianNao hPuDianNaoi [42] is designed for seven representative machine learning techniques: k-means, k-NN, na¨ıve Bayes, ”
• PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference (2019, background): “Digital accelerators have varied in their degree of flexibility, ranging from custom accelerators specialized for a particular field [14, 79, 101, 114], to accelerators that are fully programmable via an ISA [61, 71, 72, 105, 119].”
• Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “PuDianNao [9] is an accelerator designed for machine learning, but does not support CNNs.”
• AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “[17], TrueNorth [18–20], MT-spike [21], PT-spike [22] DNN Co-processor NPU [23], DianNao-family [24–27], Cambricon [28], Cambricon-x [29], TPU [30,31], ScaleDeep [32], Stripes [33], Neural Cache [123,124], Diffy [125] FPGA FPGA-DCNN [34], Embedded-FPGA-CNN [35], FPGA-Exploration [36],…”
• A^3: Accelerating Attention Mechanisms in Neural Networks with Approximation (2020, background): “CNN accelerators for custom ASIC or FPGA device [1], [2], [3], [61], [62], [63], [64], [65], [66], [67] and RNN accelerators [3], [68], [69], [70] are proposed to accelerate NN processing by exploiting massive parallelism and optimizing data movements.”
• A Configurable Cloud-Scale DNN Processor for Real-Time AI (2018, background): “The “DianNao” family of AI processors [4], [20], [33]– [35] span designs targeting small embedded clients to AI supercomputing, for both training and serving.”
• FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “Another member of the DianNao family, called PuDianNao [113], has been designed using TSMC 65nm process to support multiple techniques and scenarios of machine learning (ML).”
• ASIC Clouds: Specializing the Datacenter (2016, background): “ASIC Cloud-worthy accelerators with planet-scale applicability are numerous, including those targeting graph processing [28], database servers [29], Web Search RankBoost [30], Machine Learning [31, 32], gzip/gunzip [33] and Big Data Analytics [34].”
• From high-level deep neural models to FPGAs (2016, background): “PuDianNao [20] is an ASIC accelerator for machine learning algorithms but lacks deep convolutional networks support.”
• Graphicionado: A high-performance and energy-efficient accelerator for graph analytics (2016, background): “Example domain-specific accelerators in machine learning (PuDianNao [31], Tabla [34]) and databases (Q100 [52], Widx [27]) share the common principle with Graphicionado in that they identify the key characteristics and bottlenecks of applications in a specific domain and try to overcome them with ef”
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars (2016, background): “The PuDianNao accelerator [41] focuses on a range of popular machine learning algorithms and constructs common computational primitives.”
• A high performance FPGA-based accelerator for large-scale convolutional neural networks (2016, background): “Hence, general purpose processors are not so efficient while a number of CNN implementations based on GPU [1], FPGA [7, 8, 9, 10, 11, 12, 13, 14, 15] even ASIC [16, 17, 18, 19] have been proposed.”