Stripes: Bit-serial deep neural network computing

By Patrick Judd, Jorge Albericio, Andreas Moshovos. Micro, 2016

413 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/5bfecd14937da569eabec0afea710db846d3899b

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Artificial Intelligence

In Computer Vision and Pattern Recognition

In Hardware and Architecture

Citations in the corpus

ReLeQ : A Reinforcement Learning Approach for Automatic Deep Quantization of Neural Networks (2020, methodology): “To further demonstrate the energy and performance benefits of the solution found by RELEQ, we evaluate it on Stripes [6], a custom accelerator designed for DNNs, which exploits bit-serial computation to support flexible bitwidths for DNN operations.”
Weighted-Entropy-Based Quantization for Deep Neural Networks (2017, methodology): “NVIDIA P40 and P4 [2] which support 8-bit integer arithmetic or Stripes [14] which provides execution time and energy consumption proportional to the bitwidth.”
A^3: Accelerating Attention Mechanisms in Neural Networks with Approximation (2020, background): “CNN accelerators for custom ASIC or FPGA device [1], [2], [3], [61], [62], [63], [64], [65], [66], [67] and RNN accelerators [3], [68], [69], [70] are proposed to accelerate NN processing by exploiting massive parallelism and optimizing data movements.”
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices (2018, background): “Support for reduced precision has been demonstrated in recent hardware implementations, including Envision [15], Thinker [16], UNPU [17], Loom [18], and Stripes [19].”
The Architectural Implications of Facebook's DNN-Based Personalized Recommendation (2019, neutral): “variables [20, 26, 28, 37, 44]), and from system-level techniques (e.”
A Configurable Cloud-Scale DNN Processor for Real-Time AI (2018, background): “Other approaches also explore elision of unnecessary computation at the bit-level [37]–[39].”
UNIQ (2018, methodology): “[15] rely on bit-serial compute units and on the parallelism that is naturally present within CNNs to improve performance and energy with no accuracy loss.”
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2018, background): “Stripes [40] leverages bit-serial computation for inner product calculation to accelerate DNNs.”
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey (2020, methodology): “Two ways are utilized in this context: bit-serial [12], [278] and bit-decomposed [279], which are depicted in Figs.”
MASR: A Modular Accelerator for Sparse RNNs (2019, methodology): “We then simplify the neural networks to establish an efﬁcient baseline RNN for ASR.”
Efficient Processing of Deep Neural Networks: A Tutorial and Survey (2017, background): “, 9 b for [127] and [128]).”
Gist: Efficient Data Encoding for Deep Neural Network Training (2018, methodology): “Many HW accelerators have been designed employing limited precision and leveraging sparsity to reduce computational and memory requirements [17], [5], [6], [35], [29], [38], [47], [2].”
Machine Learning at Facebook: Understanding Inference at the Edge (2019, background): “Recent work on hardware for machine learning and efficient training and inference has substantially advanced the state-of-the-art [41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77].”
Scalpel: Customizing DNN pruning to the underlying hardware parallelism (2017, neutral): “For hardware-based methods, different ASIC designs [2, 5, 7, 8, 10, 14, 18, 25, 27, 33, 36, 37] and tools for accelerating DNN on existing platform have been proposed.”
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, background): “Stripes [123] is an implementation of variable bit width with bit-serial computation.”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, neutral): “…[21], PT-spike [22] DNN Co-processor NPU [23], DianNao-family [24–27], Cambricon [28], Cambricon-x [29], TPU [30,31], ScaleDeep [32], Stripes [33], Neural Cache [123,124], Diffy [125] FPGA FPGA-DCNN [34], Embedded-FPGA-CNN [35], FPGA-Exploration [36], OpenCL-FPGA-CNN [37] [126], Caffeine…”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, methodology): “UNPU [39] fabricates a bit-serial DNN accelerator at 65 nm, similar to Stripes [2].”