PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference
By Aayush Ankit, I. E. Hajj, S. R. Chalamalasetti, Geoffrey Ndu, M. Foltin, R. S. Williams, P. Faraboschi, Wen-mei W. Hwu, John Paul Strachan, Kaushik Roy and 1 more. International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
482 citations recorded by the source corpus.
Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications. We present the Programmable Ultra-efficient Memristor-based Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability. We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores. We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of 577 GOPS/s/mm 2 and 837~GOPS/s/W, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to 2,446× energy and 66× latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/d74bdbc0bce8ff90e815c74368cdac49b0eb4185
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In Electrical and Electronic Engineering
Citations in the corpus
- A compute-in-memory chip based on resistive random-access memory (2022, unknown): “Although there are studies on such full-chip architecture and scheduling 37,38,53 , they are outside the scope of this study.”
- AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “[94], EMAT [95], ReRAM-BNN [96], ZARA [97], SNrram [98], Sparse ReRAM Engine [149], RedEye [150], Quantum-SC-NN [151], FloatPIM [152], PUMA [153], FPSA [154] Toolset/Framework Data Parallelism [106], OWT [107], NEUTRAMS [100], Perform-ML [101], Adaptive-Classifier [102], DNNBuilder [103], Group…”
- Hardware implementation of memristor-based artificial neural networks (2024, unknown): “Moreover, ADC can consume up to 70 – 90% of the on-chip area of the crossbar-based computation unit, including memristive crossbar and peripheral circuits, and up to 80-88% of energy 55,154,155 .”
- Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing (2017, methodology): “Weight stationary has been agreed to be an efficient dataflow for executing DNN workloads [2], [3].”
- Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey (2020, methodology): “Besides the MVM operation, some other operations such as scalar and vector operations should be additionally supported by PEs since they are necessary for some neural network models such as RNNs but cannot be handled by the memristor array efficiently [258].”