ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars

By Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. S. Williams, Vivek Srikumar. 2016

1,990 citations recorded by the source corpus.

A number of recent efforts have attempted to design accelerators for popular machine learning algorithms, such as those involving convolutional and deep neural networks (CNNs and DNNs). These algorithms typically involve a large number of multiply-accumulate (dot-product) operations. A recent project, DaDianNao, adopts a near data processing approach, where a specialized neural functional unit performs all the digital arithmetic operations and receives input weights from adjacent eDRAM banks. This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner. While the use of crossbar memory as an analog dot-product engine is well known, no prior work has designed or characterized a full-fledged accelerator based on crossbars. In particular, our work makes the following contributions: (i) We design a pipelined architecture, with some crossbars dedicated for each neural network layer, and eDRAM buffers that aggregate data between pipeline stages. (ii) We define new data encoding techniques that are amenable to analog computations and that can reduce the high overheads of analog-to-digital conversion (ADC). (iii) We define the many supporting digital components required in an analog CNN accelerator and carry out a design space exploration to identify the best balance of memristor storage/compute, ADCs, and eDRAM storage on a chip. On a suite of CNN and DNN workloads, the proposed ISAAC architecture yields improvements of 14.8×, 5.5×, and 7.5× in throughput, energy, and computational density (respectively), relative to the state-of-the-art DaDianNao architecture.

Subfields: Electrical and Electronic Engineering

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Citations in the corpus

EIE: Efficient Inference Engine on Compressed Deep Neural Network (2016, background): “Efﬁcient implementation of convolutional layers in CNN has been intensively studied, as its data reuse and manipulation is quite suitable for customized hardware [10]–[15].”
Hardware implementation of memristor-based artificial neural networks (2024, positive): “The other method is sharing a single ADC across several columns or using a single ADC per crossbar tile 159,160 .”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, methodology): “ISAAC [26], PipeLayer [28], and Prime [27] use resistive RAM (ReRAM) for accelerating DNNs. Instruction Sets for DNNs. Cambricon [14] provides an ISA to express the different computations in a DNN using vector and matrix operations without signiﬁcant loss in efﬁ-ciency over DaDianNao.”
MASR: A Modular Accelerator for Sparse RNNs (2019, background): “However, much of the effort has been devoted to optimizing DNNs with only FC and CNN layers [8], [9], [10], [11], [13], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34].”
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks (2017, background): “A series of accelerator designs have also been proposed for CNNs [58, 59, 60, 61, 62, 63, 64, 65, 66, 24, 67].”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, positive): “…have focused on accelerating the compute-intensive, highly-regular computational patterns found in fully-connected (FC), convolution (CNN), and recurrent (RNN) neural networks [5], [6], [10], [15], [18], [24], [27], [34], [39], [42], [48], [56], [57], [59]–[61], [63]–[68], [70], [72], [73], [75].”
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, positive): “Recently, a full-fledged NN accelerator design based on ReRAM crossbars have been proposed, named ISAAC [39].”
Parallel convolutional processing using an integrated photonic tensor core (2021, methodology): “To build efficient hardware to perform the convolutional operations, one approach (originally conceived for electronic in-memory computing using memristive crossbar arrays 46,47 ) is to combine all the convolutional filters into a large filter matrix stored in memory.”
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation (2019, background): “However, application to larger DNNs has yet to be demonstrated, though numerous neuromorphic proposals have leveraged eNVMs, particularly using RRAMs for processing-in-memory architectures [5, 11, 61, 64].”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “Similar substrates can perform simple arithmetic operations in SRAM [79, 80] and arithmetic and logical operations in memristors [81, 180, 181, 182, 183].”