High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

By S. Suk, S. Lee, Sung-min Kim, E. Yoon, Min-Sang Kim, Ming Li, C. Oh, K. Yeo, Sung Hwan Kim, D. Shin and 8 more. IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005

253 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/59536383f106c6a05ec7cfcc39fcd5588650bd35

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In Biomedical Engineering

In Electrical and Electronic Engineering

Citations in the corpus

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs (2010, background): “Many groups have investigated the short-channel characteristics of Si NW FETs [7]–[10].”
Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires (2006, methodology): “Among GAA MOSFET, we published TSNWFET with excellent short channel immunity and extremely high driving current achieved by minimization of parasitic resistance [4].”
Considerations for Ultimate CMOS Scaling (2012, background): “height and width dimensions roughly the same (or even cylindrical) and atomically small (< 10 nm) dimensions [71]–[76].”
Scaling of Nanowire Transistors (2008, background): “The cylindrical nanowire MOSFETs with gate all around [3]–[9], as shown in Fig.”
Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate (2008, background): “have shown transistor data for 10-nm lateral Si wires with a full wrap gate using SiO2 as gate dielectric [3].”