An ASIC Implementation of the AES SBoxes
By Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger. The Cryptographer's Track at RSA Conference, 2002
358 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition
View Paper: https://www.semanticscholar.org/paper/593c4242cc02b94c9511cc05e67439725a5c08e1
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Artificial Intelligence
- Svetla Nikova
- Vincent Rijmen
- Stefan Mangard
- Martin Schläffer
- Thomas Popp
- David E. Evans
- Norbert Pramstaller
- Martin Feldhofer
In Computer Vision and Pattern Recognition
- Vincent Rijmen
- Svetla Nikova
- Martin Feldhofer
- Sandra Dominikus
- Johannes Wolkerstorfer
- Stefan Mangard
- Kris Gaj
- Pawel Chodowiec
Citations in the corpus
- Strong Authentication for RFID Systems Using the AES Algorithm (2004, methodology): “A more appropriate option is to calculate the substitution values using combinational logic as presented in [19].”
- Successfully Attacking Masked AES Hardware Implementations (2005, neutral): “in [19].”
- Faster Secure Two-Party Computation Using Garbled Circuits (2011, methodology): “Our second design aims to minimize the total execution time by implementing SubBytes with an efficient circuit derived from the work of Wolkerstorfer et al. [33].”
- A Side-Channel Analysis Resistant Description of the AES S-Box (2005, methodology): “However, while in [15] the inversion is performed in GF (16), we shift the inversion down to GF (4) in this article.”
- Very Compact FPGA Implementation of the AES Algorithm (2003, methodology): “Various area efficient implementations of AES S-boxes were proposed in [2] [4] [6] [8] [10] [13] [22] [23] [31].”
- Threshold Implementations Against Side-Channel Attacks and Glitches (2006, methodology): “As an example, the AES implementation of [26] uses a pipeline with two stages to implement the S-boxes.”
- Side-Channel Leakage of Masked CMOS Gates (2005, methodology): “However, for implementations of operations like the AES S-Box, nonlinear operations are crucial (see [18] and [25]).”
- CUDA Compatible GPU as an Efficient Hardware Accelerator for AES Cryptography (2007, background): “This section provides some references to previous work related to developing cryptography solutions both in dedicated hardware and on the GPU.”
- Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, methodology): “As an example, the AES implementation of [42] uses a pipeline with two stages to implement the S-boxes.”
- A Very Compact S-Box for AES (2005, neutral): “, [13], [14], [17], and [2].”