A Very Compact S-Box for AES

By David Canright. Workshop on Cryptographic Hardware and Embedded Systems, 2005

618 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition

View Paper: https://www.semanticscholar.org/paper/1442dff91bf7a583cb776b024e5375f29b21b239

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Citations in the corpus

Foundations of garbled circuits (2012, methodology): “We use a different S-box circuit [25] than HEKM, which results in a smaller AES circuit.”
Fully homomorphic SIMD operations (2012, methodology): “For example the approach in [4] transforms the polynomial bases into a “nice” normal basis and then decomposes the arithmetic for inversion into F24 and then F22 operations.”
Midori: A Block Cipher for Low Energy (2015, methodology): “It can be seen that the successive instances of the LUT based S-box which has a delay of around 2.1 ns consumes much less energy as compared to the Canright S-box which has a delay of around 2.9 ns.”
Provably Secure Higher-Order Masking of AES (2010, methodology): “As an illustration, masking the compact circuit for the AES S-box described in [5] would multiply its size (in terms of number of gates) by 7 for d = 2, by 14 for d = 3 and by 22 for d = 4 (without taking the random bits generation into account).”
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core (2006, methodology): “In our core we use the S-box design of [1], which presents the most compact ASIC S-box solution according to our knowledge.”
The PHOTON Family of Lightweight Hash Functions (2011, methodology): “P256 256 8 4 12 [0, 1, 3, 7, 15, 14, 12, 8] x 4 + x + 1 (2, 4, 2, 11, 2, 8, 5, 6)”
Pushing the Limits: A Very Compact and a Threshold Implementation of AES (2011, methodology): “On the other hand, several masking schemes have been proposed to create a masked AES S-box using either multiplicative or additive approaches.”
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches (2011, methodology): “This tower field approach is often used in implementations of the AES S-box [7].”
Efficient Garbling from a Fixed-Key Blockcipher (2013, methodology): “We use a different S-box circuit [11] than HEKM, which results in a smaller AES circuit.”
Faster and Timing-Attack Resistant AES-GCM (2009, methodology): “The starting point of our implementation is the compact hardware S-Box proposed by Canright [11], requiring 120 logic gates, and its recent improvements by Boyar and Peralta [10], which further reduce the gate count to 117.”
Accelerating NTRU based homomorphic encryption using GPUs (2014, methodology): “In [34], the authors introduce an efficient inversion implementation by converting the input from GF (28) into a tower field representation GF (((22)2)2) using an isomorphism.”
$\textnormal{\textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms (2012, methodology): “While AES has been widely deployed and we can see constant efforts for smallfootprint AES, such as [13, 30, 39], AES is often inappropriate for such small devices due to their size/power/memory constraints.”