Very Compact FPGA Implementation of the AES Algorithm
By Pawel Chodowiec, Kris Gaj. Workshop on Cryptographic Hardware and Embedded Systems, 2003
367 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition
View Paper: https://www.semanticscholar.org/paper/4d5e15c080dde7e5c50ae2697ee56d29218235b1
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Artificial Intelligence
- Timo D. Hämäläinen
- Marko Hännikäinen
- Timo Alho
- Panu Hämäläinen
- Martin Feldhofer
- Sandra Dominikus
- David Canright
- Johannes Wolkerstorfer
In Computer Vision and Pattern Recognition
- Timo D. Hämäläinen
- Marko Hännikäinen
- Timo Alho
- Panu Hämäläinen
- Martin Feldhofer
- Sandra Dominikus
- David Canright
- Johannes Wolkerstorfer
Citations in the corpus
- Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core (2006, methodology): “SubBytes can be implemented either by computing the substitution [1,4–6,12,14] or using table lookups [2] [3] [7] [12].”
- Strong Authentication for RFID Systems Using the AES Algorithm (2004, methodology): “To name some: [14,1] are FPGA implementations and [10,16] are ASIC implementations of AES which care about hardware efficiency.”
- A Very Compact S-Box for AES (2005, background): “Some approaches seek to maximize throughput, e.g., [7], [16] and [3]; others minimize power consumption, e.g., [8]; and yet others minimize circuitry, e.g., [13], [14], [17], and [ 2 ].”