EPIC: Ending Piracy of Integrated Circuits

By Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov. Design, Automation and Test in Europe, 2008

697 citations recorded by the source corpus.

Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/48994fc4782375018e8ac314ba5b47b6984b7f0c

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Citations in the corpus

Fault Analysis-Based Logic Encryption (2015, methodology): “Hamming distancebetween the outputs of designs on applying the correct key and a randomwrong key: (a) Random insertion of XORs in ISCAS designs [6], [7], [11], (b) fault analysis-based insertion of XORs in ISCASdesigns, (c) random insertion of XORs inOpenSPARC [6], [7], [11], and (d) fault analysis-”
SARLock: SAT attack resistant logic locking (2016, background): “Logic locking 1 is a set of techniques that thwart IP piracy, overbuilding, and reverse engineering attacks by locking a design with a secret key [6], [10]– [12].”
Preventing IC Piracy Using Reconfigurable Logic Barriers (2010, methodology): “Key creation Two previous combinational-locking schemes use two-input XOR and XNOR gates inserted on random wires throughout the design.(2,3) We increase the flexibility of combinational locking by using k-input lookup tables (LUTs), and we create selection heuristics to optimize lock placement.”
AppSAT: Approximately deobfuscating integrated circuits (2017, methodology): “Traditional methods for logic encryption in literature include: XOR/XNORing wires selected from the circuit with key-bits [2], [11], [12], replacing gates in the circuit with look-up-tables (LUTs) that store key-bits [13], [14], inserting multiplexors (MUXs) [11] or switch-boxes (SB) [15] that are c”
Security analysis of integrated circuit camouflaging (2013, background): “In combinational logic obfuscation, XOR/XNOR gates are introduced to conceal the functionality of a design [30].”
On Improving the Security of Logic Locking (2016, background): “…Investment Company under Grant 2013-HJ-2440-S4, in part by the New York University/New York University Abu Dhabi Center for Research in Information Security Studies and Privacy, and in part by the National Science Foundation, and Computing and Communication Foundations under Grant 1319841.”
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection (2009, background): “Usually, this is implemented by including a locking mechanism in the IC [11], [12].”
A Primer on Hardware Security: Models, Methods, and Metrics (2014, background): “Section VII concludes the paper.”
Evaluating the security of logic encryption algorithms (2015, methodology): “EPIC [19] is the orginal proposal for logic encryption and it inserts XOR and XNOR gates at randomly chosen locations in the IC.”
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain (2014, methodology): “This locking is mostly done in three ways: 1) initializing ICs to a locked state on power-up [20]; 2) combinational locking by scattering xor gates randomly throughout the design [71]–[73]; and 3) adding a finitestate machine (FSM) which is initially locked and can be unlocked only with the correct ”