On Improving the Security of Logic Locking

By Muhammad Yasin, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016

310 citations recorded by the source corpus.

Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/ebbe5d0df5ab72a842f16f21bb7217bdba295589

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Cellular and Molecular Neuroscience

1. Ozgur Sinanoglu
2. Jeyavijayan Rajendran
3. Muhammad Yasin

In Electrical and Electronic Engineering

1. Muhammad Yasin
2. Ozgur Sinanoglu
3. Jeyavijayan Rajendran
4. M. Ashraf
5. M. Nabeel
6. A. Sengupta

In Hardware and Architecture

1. Muhammad Yasin
2. Ozgur Sinanoglu
3. Jeyavijayan Rajendran
4. M. Ashraf
5. M. Nabeel
6. A. Sengupta
7. Ankit Mondal
8. Abhishek Chakraborty

Citations in the corpus

• Hardware-Assisted Intellectual Property Protection of Deep Learning Models (2020, background): “In our proposed HPNN framework, licenses are distributed in the form of trustworthy hardware devices which securely embed the secret HPNN key on-chip [5], [25].”
• Provably-Secure Logic Locking: From Theory To Practice (2017, background): “In [34], two key bits are considered pairwise-secure i the sensitization of one key bit cannot be done without controlling the other key bit and vice versa. e same paper presents SLL that maximizes key bits that are all pairwise-secure.”