HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

By Rajat Subhra Chakraborty, Swarup Bhunia. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009

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Fault Analysis-Based Logic Encryption (2015, methodology): “Hamming distancebetween the outputs of designs on applying the correct key and a randomwrong key: (a) Random insertion of XORs in ISCAS designs [6], [7], [11], (b) fault analysis-based insertion of XORs in ISCASdesigns, (c) random insertion of XORs inOpenSPARC [6], [7], [11], and (d) fault analysis-”
Physical unclonable functions (2020, background): “Specifically, the ECC logic overhead is usually not properly taken into account when assessing the overhead for those applications but treated as a default part of the PUF, which may lead to underestimated overhead assessment for the targeted applications 84–86 .”
Security analysis of integrated circuit camouflaging (2013, background): “In sequential logic obfuscation, additional logic (black) states are introduced in the finite state machine (FSM) of a design [23, 29].”
A Primer on Hardware Security: Models, Methods, and Metrics (2014, background): “Section VII concludes the paper.”
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain (2014, methodology): “This locking is mostly done in three ways: 1) initializing ICs to a locked state on power-up [20]; 2) combinational locking by scattering xor gates randomly throughout the design [71]–[73]; and 3) adding a finitestate machine (FSM) which is initially locked and can be unlocked only with the correct ”