Preventing IC Piracy Using Reconfigurable Logic Barriers
By Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno. IEEE Design & Test of Computers, 2010
322 citations recorded by the source corpus.
Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/ec3d44308ab5fc8a1db3c8246e350dc3dfbc2002
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Cellular and Molecular Neuroscience
- Ozgur Sinanoglu
- Ramesh Karri
- Jeyavijayan Rajendran
- Muhammad Yasin
- Sharad Malik
- Pramod Subramanyan
- M. Tehranipoor
- Youngok Pino
In Electrical and Electronic Engineering
- Ozgur Sinanoglu
- Muhammad Yasin
- Jeyavijayan Rajendran
- Ramesh Karri
- M. Tehranipoor
- M. Ashraf
- M. Nabeel
- A. Sengupta
In Hardware and Architecture
- Ozgur Sinanoglu
- Muhammad Yasin
- Jeyavijayan Rajendran
- Ramesh Karri
- M. Tehranipoor
- M. Ashraf
- M. Nabeel
- A. Sengupta
Citations in the corpus
- On Improving the Security of Logic Locking (2016, methodology): “On applying the correct values of the keys (K1 = 0 and K2 = 1), the design will produce a correct output; otherwise, it will produce a wrong output.”
- SARLock: SAT attack resistant logic locking (2016, methodology): “Researchers have previously used the terms " logic obfuscation " [6]–[9] and " logic encryption " [10] for this purpose.”
- Provably-Secure Logic Locking: From Theory To Practice (2017, background): “Traditional logic locking techniques choose key gate locations based on various gate selection algorithms, such as random (RLL) [38], fault analysis-based (FLL) [5, 36], and stronginterference-based logic locking (SLL) [34, 59].”
- Evaluating the security of logic encryption algorithms (2015, background): “[1] (“DTC’10/LUT”) insert a set of lookup tables (LUTs) to the IC such that every path from an input to an output goes through a lookup table.”
- A Primer on Hardware Security: Models, Methods, and Metrics (2014, unknown): “Section VII concludes the paper.”
- Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain (2014, methodology): “In addition to unique identification, active metering approaches lock each IC until it is unlocked by the IP holder [20], [69]–[73].”
- Security analysis of integrated circuit camouflaging (2013, background): “Obfuscation is also performed by inserting memory elements [33].”
- Fault Analysis-Based Logic Encryption (2015, methodology): “Logic encryption techniques can thwart an untrusted foundry from illegally copying, reverse engineering, overproducing the IC design [3], [5]–[8], [11], and Trojan insertion [12].”