Fault Analysis-Based Logic Encryption

By Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, G. Rose, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri. IEEE transactions on computers, 2015

425 citations recorded by the source corpus.

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AppSAT: Approximately deobfuscating integrated circuits (2017, methodology): “Traditional methods for logic encryption in literature include: XOR/XNORing wires selected from the circuit with key-bits [2], [11], [12], replacing gates in the circuit with look-up-tables (LUTs) that store key-bits [13], [14], inserting multiplexors (MUXs) [11] or switch-boxes (SB) [15] that are c”
Provably-Secure Logic Locking: From Theory To Practice (2017, methodology): “Aack RLL FLL SLL AntiSAT SARLock TTLock Proposed [38] [5, 36] [34] [52] [55] [61] SFLL Sensitization [34] 7 7 3 3 3 3 3 SAT [44] 7 7 7 3 3 3 3 AppSAT [40] 7 7 7 7 7 7 3 Removal/SPS [57] 3 3 3 7 7 3 3 Original circuit IN OUT”
SARLock: SAT attack resistant logic locking (2016, methodology): “Researchers have previously used the terms " logic obfuscation " [6]–[9] and " logic encryption " [10] for this purpose.”
Evaluating the security of logic encryption algorithms (2015, background): “[18] also propose two algorithms that insert XOR (“ToC’13/xor”) and MUX (“ToC’13/mux”) gates at locations which maximize the Hamming distance between correct and incorrect outputs.”