Vertical high-mobility wrap-gated InAs nanowire transistor
By Tomas Bryllert, Lars-Erik Wernersson, L. Fröberg, Lars Samuelson. IEEE Electron Device Letters, 2006
298 citations recorded by the source corpus.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/03e9e8c2d7ff8d5878e10e5073d2b8cdb2ad0dfa
How researchers see this paper
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In Biomedical Engineering
- Magnus Borgström
- J. Wallentin
- Lars Samuelson
- Wei Dang Lu
- Ping Xie
- L. Wallenberg
- K. Deppert
- Lars-Erik Wernersson
In Electrical and Electronic Engineering
- Magnus Borgström
- J. Wallentin
- Lars Samuelson
- Wei Dang Lu
- Ping Xie
- L. Wallenberg
- K. Deppert
- Lars-Erik Wernersson
Citations in the corpus
- Vertical wrap-gated nanowire transistors (2006, methodology): “We use two different methods to form the drain contact: either an air-bridge [7, 8] (figure 5) or a contact deposited directly on the protective SiNx (figure 6).”
- In situ etching for total control over axial and radial nanowire growth (2010, background): “Recently nanowires (NWs) have attracted attention as one of the most promising ways to combine highperformance III–V materials with new functionality [1–4] and existing Si technology [5, 6].”
- Nanowire Transistor Performance Limits and Applications (2008, background): “trodes, vertical nanowire-transistors (VNWFETs) have been demonstrated [41], [109], [110] and may offer increased oncurrent due to the use of gate-all-around structure.”