A 240 G-ops/s Mobile Coprocessor for Deep Neural Networks

By Vinayak Gokhale, Jonghoon Jin, Aysegul Dundar, Berin Martini, Eugenio Culurciello. 2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2014

299 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/233b1774f28c9972df2dfcf20dfbb0df45792bd0

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Citations in the corpus

Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA (2018, methodology): “It is also proved to be an effective way in the previous work [6], [20], [21] but limited to 16-bit or 12-bit.”
Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations (2016, background): “These efficiency numbers are about 5 orders of magnitude better than state-of-the-art CPU and GPU performance metrics (Gokhale et al., 2014).”
Conversion of Continuous-Valued Deep Networks to Efficient Event-Driven Networks for Image Classification (2017, methodology): “Multi-layered spiking networks have been implemented on digital commodity platforms such as FPGAs (Neil and Liu, 2014; Gokhale et al., 2014), but spiking networks with more than tens of thousands of neurons can be implemented on large-scale neuromorphic spiking platforms such as TrueNorth (Benjamin…”
Deep Learning in Mobile and Wireless Networking: A Survey (2018, methodology): “Fog computing nn-X [107], ncnn [108], Kirin 970 [109], Core ML [110] Mobile devices Support edge-based deep learning computing Medium Low Medium (hardware)”
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory (2016, background): “While there are architectures that attempt to achieve performance and scalability by reducing the processing units [3]–[5], [7], [8], the overall system performance is often limited due to insufficient memory bandwidth and network latency.”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “Due to their insatiable demand for compute power, naturally, both the research community [1–28] as well the industry [29–31] have turned to accelerators to accommodate modern DNN computation.”
SqueezeNext: Hardware-Aware Neural Network Design (2018, methodology): “Weight Stationary WS is the most common method used in many notable neural network accelerators [5, 4, 7, 18, 2].”
Coreset-Based Neural Network Compression (2018, background): “This characteristic of deep CNN architectures reduces their portability, and poses a severe bottleneck for implementation in resource constrained environments [17].”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, background): “In addition, the 16-bit implementation of Angel-Eye on XC7Z045 is 6× faster and 5× higher in power efficiency than peer FPGA implementation on the same platform [148].”
Compression of Deep Neural Networks on the Fly (2015, background): “Importing CNNs onto embedded platforms [10], the recent trend toward mobile computing, has a wide range of application impacts.”
From high-level deep neural models to FPGAs (2016, methodology): “[27] propose a mobile co-processor for DNNs and evaluate it on a Zynq board.”
Compressing Deep Convolutional Networks using Vector Quantization (2014, background): “Importing CNN onto embedded platforms (Gokhale et al., 2013; Culurciello et al., 2013), the recent trend toward mobile computing, has a wide range of application impacts.”
CaffePresso: An optimized library for Deep Learning on embedded accelerator-based platforms (2016, background): “Unlike solutions (FPGAs [10, 14, 7], GPUs [13]) using abundant hardware resources, embedded solutions are severely constrained by the limited capacity of logic, on-chip memory and communication bandwidth.”
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights (2016, background): “Even though most approaches work with ﬁxed-point operations, the number of quantization bits is still kept at 24 bits([30], [29]) or 16 bits([12], [13], [31], [33], [34]).”
Dynamic Deep Neural Networks: Optimizing Accuracy-Efficiency Trade-offs by Selective Execution (2017, background): “ redundancy in data or computation in a way that is input independent. The strategies include approximating layers with simpler functions [12,34,21], using number representations of limited precision [7,14,16], and pruning network parameters [18,22,17]. The other line of work exploits the fact that ”
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks (2016, unknown): “Keywords FPGA, OpenCL, Convolutional Neural Networks, Optimization.”
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration (2016, background): “Even though most approaches work with ﬁxed-point operations, the number of quantization bits is still kept at 24-bit [28], [40] or 16-bit [17], [18], [27], [42], [45].”
Memory and Information Processing in Neuromorphic Systems (2015, background): “…system to carry out computation, and Section V will present an example of a neuromorphic processor that implements such mechanisms and that can be used to endow autonomous behaving systems with learning abilities for adapting to changes in the environment and interacting with it in real-time.”