Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

By Naveen Suda, Vikas Chandra, Ganesh S. Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao. Symposium on Field Programmable Gate Arrays, 2016

535 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/b4eac8295c90dbfb7d8d22ba560e025621287c58

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Citations in the corpus

A high performance FPGA-based accelerator for large-scale convolutional neural networks (2016, methodology): “Thus, the operation number and weight number for each layer in the AlexNet model are collected as shown in Fig.2 and Fig.3, which reflects the computation-intensive feature of CONV layers and the memory-intensive feature of FC layers.”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “Mapping DNNs computational operations to matrix multiplication has been widely applied in prior studies [80], [132], [174].”
Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks (2016, methodology): “The work in [22] transforms a convolution layer into a regular matrix-multiplication (MM) in the FCN layer, and implements an MM-like accelerator for both layers.”
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs (2017, background): “3062207 roofline model to identify the optimal design option from a large design space, while the authors in [7, 8] propose analytical models to realize this goal.”
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA (2016, methodology): “They use multiple RBM processing modules in parallel, with each module responsible for a relatively small number of nodes.”
Maximizing CNN accelerator efficiency through resource partitioning (2016, methodology): “[28] develop an OpenCLbased HLS tool to implement CNN accelerators that use different modules for different kinds of layers, but all convolutional layers are computed with a single CLP.”
DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs (2018, background): “, [14] and [16]) have stored input feature maps on chip to achieve higher throughput and avoid complicated data movement.”
Hello Edge: Keyword Spotting on Microcontrollers (2017, background): “Previous research [33, 34, 35] have shown that fixed-point weights is sufficient to run neural networks with minimal loss in accuracy.”
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer (2017, background): “A modern CNN contains hundreds of megabytes of weights, leading to a severe off-chip bandwidth bottleneck [7], [10]–[14].”
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs (2018, unknown): “VGG-SVD[39] AlexNet[47] VGG16[48] VGG16 [40] DoReFa[42] FINN-R [41] Ours”
From high-level deep neural models to FPGAs (2016, methodology): “[39, 40] present implementations of accelerators for particular DNN models.”
CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs (2018, background): “Although precision requirements for different networks or network layers can vary [7], it is hard for the CPU to operate on data types with varying bit-width.”
Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, background): “While there has been significant prior work on scheduling a single DNN model efficiently over one (or more distributed) accelerators [65, 95, 100, 102, 115, 122], scheduling multiple models simultaneously is relatively unexplored, and is the focus of this work.”
A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, methodology): “91], and ImageNet [1827]. Evaluations of how well neuromorphic systems implement AlexNet, a popular convolutional neural network architecture for image classiﬁcation, have also been conducted [1056], [1074]. Examples of images from the MNIST data set, the CIFAR10, and the SVHN data set are given in ”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “…[32], Stripes [33], Neural Cache [123,124], Diffy [125] FPGA FPGA-DCNN [34], Embedded-FPGA-CNN [35], FPGA-Exploration [36], OpenCL-FPGA-CNN [37] [126], Caffeine [38], DeepBurning [39], FPGA-DPCNN [40], TABLA [41], DNNWEAVER [42], FP-DNN [43], FPGA-LSTM [44], ESE [45], FPGA-Dataﬂow [46],…”