Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
By J. Kavalieros, Brian Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, Marko Radosavljevic and 4 more. 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 2006
231 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/223db2b6f0d02c7f832dcccb52ab314f4878883d
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In Electrical and Electronic Engineering
Citations in the corpus
- Soft Error Susceptibilities of 22 nm Tri-Gate Devices (2012, methodology): “M ULTI-GATE FETs, such as FinFETs and Tri-Gate FETs have long been advertised as the most promising candidates to extendCMOS scaling [1], [2].”
- Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia (2008, background): “available today [47] (with pretty good uniformity and quality) and can still be thinned further by oxidation; 2) etched Fins—for DELTA [48], FinFET [49], or trigate transistors [73], very thin films have been demonstrated, but due to the use of sublithographic resolution techniques (Tsi needs to be ”
- Impact of Line-Edge Roughness on FinFET Matching Performance (2007, background): “On the other hand, the introduction of alternative transistor architectures, such as FinFET, can significantly improve transistor performance at short dimensions [1], [2].”
- Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm (2011, methodology): “JAM and IM n-channel devices of EOT = 1 nm were fabricated using an SOI trigate process similar to the one described in [5].”
- Considerations for Ultimate CMOS Scaling (2012, background): “sides and the top [58]–[60]), Pi-Gates (the side gates extend”