High-voltage normally off GaN MOSFETs on sapphire substrates

By K. Matocha, T. Paul Chow, R. Gutmann. IEEE Transactions on Electron Devices, 2005

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Enhancement-Mode n-Channel GaN MOSFETs on p and n-GaN/Sapphire Substrates (2006, methodology): “GaN MOSFETs on n GaN epilayer have been cleaned with RCA clean and diluted HCl before 600nm-thick fabricated by several groups recently [2-6].”
Normally Off GaN MOSFET Based on AlGaN/GaN Heterostructure With Extremely High 2DEG Density Grown on Silicon Substrate (2010, result): “extracted in the linear region (at Vd = 0.1 V), as shown in Fig. 4(a), which is the highest value ever reported for the GaN MOSFET, and the extracted subthreshold slope was 317 mV/dec, which is comparable to the values reported by others [7]‐[ 10 ].”
Materials and processing issues in vertical GaN power electronics (2017, methodology): “In [50], the channel of the GaN MOSFET is fabricated on (0001) plane, where spontaneous and piezo-electric polarization effects are present.”