Extracting secret keys from integrated circuits

By D. Lim, Jae W. Lee, Blaise Gassend, G. Suh, Marten van Dijk, Srini Devadas. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2005

1,048 citations recorded by the source corpus.

Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires and transistors across integrated circuits (ICs) in manufacturing processes to build unclonable secret keys. We fabricated arbiter-based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of inter-chip variation exists to enable each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. We show that arbiter-based PUFs are realizable and well suited to build, for example, key-cards that need to be resistant to physical attacks.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/fe195a79c748c2f883e4eebef4402dc6c612399b

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Citations in the corpus

Physical Unclonable Functions for Device Authentication and Secret Key Generation (2007, background): “(For an analysis of modelbuilding on arbiter PUFs see [8].”
Physical Unclonable Functions and Applications: A Tutorial (2014, methodology): “These efforts included xor arbiter PUFs, lightweight secure PUFs, and feedforward arbiter PUFs [8], [16], [17], [22], [39].”
Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions (2010, methodology): “They use the same delay circuit as in the basic arbiter PUF design from [29, 28] which is hence also susceptible to model-building attacks.”
Modeling attacks on physical unclonable functions (2010, methodology): “raise the attacker’s complexity further, for example adding nonlinearity (such as AND and OR gates that correspond to MAX and MIN operators [17]).”
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain (2014, background): “In [63], [90], and [91], a delay PUF exploiting the random variations in delays of wires and gates on silicon was proposed.”
Extended abstract: The butterfly PUF protecting IP on every FPGA (2008, methodology): “[13] introduce arbiter based PUFs which use a differential structure and an arbiter to distinguish the difference in the”
Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive (2011, methodology): “The Arbiter PUF (APUF) employs a pair of configurable delay paths stimulated by an input signal, and the skew in propagation delay between the two paths due to process variation is detected by an edge-sensitive latch or arbiter [9].”
Aegis: A Single-Chip Secure Processor (2007, background): “Two Master theses [38, 74] provide good summaries of all previous work on PUFs.”
Physically Unclonable Functions (2012, background): “[48, 80, 83] propose to implement the two delay paths as a chain of switch blocks.”
FPGA Intrinsic PUFs and Their Use for IP Protection (2007, methodology): “Therefore Lim et al. [25] introduce the concept of arbiter based PUF which uses a diﬀerential structure - two identical delay paths - and an arbiter to distinguish the diﬀerence in the delay between the paths.”
A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions (2011, methodology): “In any case, even the Arbiter PUF shows a very low probability of misidentification.”