3D stacked IC demonstration using a through Silicon Via First approach
By J. V. Olmen, A. Mercha, G. Katti, Cedric Huyghebaert, J. V. Aelst, E. Seppala, Zhao Chao, S. Armini, J. Vaes, R. C. Teixeira and 20 more. 2008 IEEE International Electron Devices Meeting, 2008
152 citations recorded by the source corpus.
Subfields: Automotive Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/8ba00323c270462d80e805d349879ba291cdeadf
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In Electrical and Electronic Engineering
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Citations in the corpus
- Design Issues and Considerations for Low-Cost 3-D TSV IC Technology (2010, background): “DC Resistance and low frequency capacitance are fundamental electrical parameters of TSVs. Measure of TSV resistance between the top of the TSV and the landing pad provides information on the quality of the vertical electrical connection established by the bonding of the staked dies.”
- Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs (2010, methodology): “The assumption is not valid in state-of-the-art TSV technologies, where the via-hole etching and isolation SiO2 is usually formed after the front-end-of-line processes [6], [8], because the Si-SiO2 interface charge, which is induced by plasma damage during via-hole etching or dielectric deposition”
- Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs (2010, methodology): “In the 3-D TSV first approach [7], TSVs are fabricated after FEOL processing and before BEOL processing and enable the interconnection between the Top Metal of the bottom tier and Metal1 of the top tier, as shown in the cross section of Fig.”