Relaxing non-volatility for fast and energy-efficient STT-RAM caches
By IV ClintonWillsSmullen, Vidyabhushan Mohan, Anurag Nigam, S. Gurumurthi, Mircea R. Stan. 2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011
439 citations recorded by the source corpus.
Subfields: Atomic and Molecular Physics, and Optics, Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/1600c3ed12301b06a1107a68c2de84fb3582a918
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Atomic and Molecular Physics, and Optics
In Computer Networks and Communications
- Onur Mutlu
- Mahmut Taylan Kandemir
- Naveen Muralimanohar
- Rajeev Balasubramonian
- Anand Sivasubramaniam
- Emre Kultursay
- Yuan Xie
- Zhang Tao
In Hardware and Architecture
- Onur Mutlu
- Mahmut Taylan Kandemir
- Rajeev Balasubramonian
- Naveen Muralimanohar
- Anand Sivasubramaniam
- Emre Kultursay
- Yuan Xie
- Cong Xu
Citations in the corpus
- Overcoming the challenges of crossbar resistive memory architectures (2015, background): “Moreover, some prior work [44, 47] propose trading-off retention time to improve write latency.”
- NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory (2012, background): “For example, Smullen et al. relaxed the retention time requirement to improve the timing and energy profile of STT-RAMs [16].”
- Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Yet, STT-RAM technology has so far only been explored as an SRAM substitute for on-chip caches [27], [53], [56], [57], [62], but has not been considered as a candidate for main memory.”