The M5 Simulator: Modeling Networked Systems

By N. Binkert, Ronald Dreslinski Jr., Lisa R. Hsu, Kevin T. Lim, A. Saidi, Steven K. Reinhardt. IEEE Micro, 2006

876 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/bd2eb55d5c497b4a02b992bab4e4e0ec289a2e95

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Citations in the corpus

Page placement in hybrid memory systems (2011, methodology): “In the first step, we use M5 [5] to collect memory access (LLC misses and write-backs) traces from our workloads runn ing on an 8-core server.”
An Evaluation of High-Level Mechanistic Core Models (2014, methodology): “The new window and old window are structures that allow for the approximation of performance in the interval simulation methodology.”
PDRAM: A hybrid PRAM and DRAM main memory system (2009, methodology): “For our experimental evaluation we use the M5 architecture simulator [4].”
The gem5 Simulator: Version 20.0+ (2020, methodology): “1.1 The past, present, and future of gem5 The gem5 simulator was born when the m5 simulator [20] created at University of Michigan merged with the GEMS simulator [50] from University of Wisconsin.”
Packet Chasing: Spying on Network Packets over a Cache Side-Channel (2019, positive): “We model this architecture using the gem5 [77] architectural simulator.”
McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures (2009, positive): “By using McPAT together with M5 [6], another cycleaccurate performance simulator, we also studied clustering trade-offs of manycore processors with 16 OOO cores at 22nm running at 3.”
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation (2011, background): “Academic simulators, such as M5 [4], GEMS [20] and PTLSim [32] are not truly cycle-accurate compared to real hardware, and therefore they are typically faster, with simulation speeds in the tens to hundreds of KIPS (kilo simulated instructions per second) range.”
Corona: System Implications of Emerging Nanophotonic Technology (2008, positive): “The simulator, which is based on the M5 framework [4], takes an trace-driven approach to processing memory requests.”
Producing wrong data without doing anything obviously wrong! (2009, methodology): “We repeated a selection of the above experiments on the m5 simulator using the O3CPU model [2].”
ZSim: fast and accurate microarchitectural simulation of thousand-core systems (2013, background): “Emulation is the natural choice when the simulated ISA is diﬀerent from the host’s, and many simulators choose it to be portable. gem5 [4, 5, 25], Flexus [51] and MARSS [29] are current representative emulation-based systems.”
Relaxing non-volatility for fast and energy-efficient STT-RAM caches (2011, methodology): “We model a 4GHz processor with four out-of-order cores using M5 [5].”
The gem5 simulator (2011, methodology): “Both the O3 and InOrder models are “execute-in-execute” designs [4].”