PDRAM: A hybrid PRAM and DRAM main memory system
By Gaurav Dhiman, Raid Ayoub, Tajana Šimunić. 2009 46th ACM/IEEE Design Automation Conference, 2009
487 citations recorded by the source corpus.
Subfields: Cognitive Neuroscience, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/bc31e7e7cd9d67c14c6dfab517877639c3d98ac6
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Citations in the corpus
- NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems (2015, result): “However, existing CPU and memory controller may reorder memory writes which makes it non-trivial to develop consistent NVM-based systems and data structures, as demonstrated in previous works [44, 53, 58, 55, 14, 12, 18, 35, 22, 46, 10, 32, 17].”
- Use ECP, not ECC, for hard failures in resistive memories (2010, background): “Of these emerging technologies, PCM has received the most research attention in the architecture literature [7, 11, 21, 22, 26, 27, 28], as it is closest to commercialization [18, 24].”
- Evaluating STT-RAM as an energy-efficient main memory alternative (2013, unknown): “Page allocation [51], page migration [14], [64], and block migration [40] are three approaches to software-exposed hybrid memory.”
- In-Memory Big Data Management and Processing: A Survey (2015, background): “With the advancement of hardware, hybrid systems which incorporate nonvolatile memories (NVMs) (e.g., SCM, PCM, SSD, Flash memory) [30], [31], [32], [118], [127], [153], [154], [155], [156] become a natural solution for achieving the speed.”
- Memory scaling: A systems architecture perspective (2013, background): “For example, should all memories be part of main memory or should some of them be used as a cache of main memory (or should there be configurability)? What technologies should be software visible? What component of the system should manage data allocation and movement? Should these tasks be done in ”