Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers

By Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt. 2007 IEEE 13th International Symposium on High Performance Computer Architecture, 2007

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SHiP: Signature-based Hit Predictor for high performance caching (2011, background): “Alternatively, studies have also shown that simply changing the re-reference prediction on cache insertions [10, 27, 29, 32] can significantly improve cache performance at very low hardware overhead.”
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013, background): “, [13, 23, 45, 52]) have been proposed within the context of CPU systems.”
Base-delta-immediate compression: Practical data compression for on-chip caches (2012, methodology): “For multi-programmed workloads we use the weighted speedup [25] as the performance metric: For bandwidth consumption we use BPKI (bytes transferred over bus per thousand instructions [27]).”
RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013, neutral): “NumberofCores 2 4 8 NumberofWorkloads 138 50 40 WeightedSpeedup[14]Improvement 15% 20% 27% InstructionThroughputImprovement 14% 15% 25% HarmonicSpeedup[35]Improvement 13% 16% 29% MaximumSlowdown[12,29,30]Reduction 6% 12% 23% MemoryBandwidth/Instruction[49]Reduction 29% 27% 28% MemoryEnergy/Instru”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, neutral): “Several prior papers investigated how to handle prefetch requests in shared resources [Ebrahimi et al. 2009, 2011a; Srinath et al. 2007].”