R. Iyer

Hardware and Architecture · with Das · 2013–2018

A researcher in the Science corpus: 2 papers; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.

Subfields

• Hardware and Architecture — 25 citations into it
• Computer Networks and Communications — 23 citations into it

Whom R. Iyer trusts

Their strongest outbound trust, strongest first, inferred from their citations.

1. Onur Mutlu (in Hardware and Architecture)

Papers from R. Iyer's perspective

Ordered by how strongly the researchers R. Iyer trusts endorse each paper. Same corpus, a different order for every researcher.

1. Rethinking the Inception Architecture for Computer Vision
2. EIE: Efficient Inference Engine on Compressed Deep Neural Network
3. Memory access scheduling (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
4. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (International Symposium on Computer Architecture)
5. Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow (Micro)
6. DaDianNao: A Machine-Learning Supercomputer
7. RAPL: Memory power estimation and capping (International Symposium on Low Power Electronics and Design)
8. NVIDIA Tesla: A Unified Graphics and Computing Architecture
9. Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems (USENIX Security Symposium)
10. Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (Micro)

Their papers

• Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2018) — 392 citations
• OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013) — 301 citations