Optimizing pipelines for power and performance

By Vijayalakshmi Srinivasan, David M. Brooks, M. Gschwind, Pradip Bose, V. Zyuban, P. Strenski, P. Emma. 2002

160 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Pradip Bose
2. Jude A. Rivers
3. Jayanth Srinivasan
4. Sarita V. Adve
5. Krste Asanovic
6. Keren Bergman
7. Assaf Shacham
8. Luca P. Carloni

In Hardware and Architecture

1. Pradip Bose
2. Krste Asanovic
3. Michael Zhang
4. Keren Bergman
5. Assaf Shacham
6. Luca P. Carloni

Citations in the corpus

• Power efficient processor architecture and the cell processor (2005, background): “Even in the face of a slowdown in transistor performance growth, this path allows for continued increases in chip performance at historical rates for at least a decade if accelerated off-chip bandwidth needs are addressed [4].”
• The case for lifetime reliability-aware microprocessors (2004, background): “Coupled with separate (prior) findings about how single processor pipeline depths (and operating clock frequencies) had reached their scaling limits [8], this class of work pointed to significant implications about future microarchitecture design.”
• Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors (2005, methodology): “A 24 FO4 processor clock cycle is assumed in this paper, representing a modern power-performance balanced pipeline design [11, 23].”
• Cooperative Caching for Chip Multiprocessors (2006, unknown): “Variable Values Workloads Multithreaded commercial workloads (OLTP, Apache, JBB, and Zeus) Multiprogrammed SPEC2000 workloads (heterogeneous and homogeneous) Multithreaded SPECOMP workloads (for VR comparison) Single-threaded MinneSPEC benchmarks (for VR comparison) System sizes 4-core and 8-core CM”
• Introduction to the Cell multiprocessor (2005, background): “A third barrier to improving performance stems from the observation that we have reached a point of diminishing return for improving performance by further increasing processor frequencies and pipeline depth [9].”
• Cell Multiprocessor Communication Network: Built for Speed (2006, background): “Performance improvements from further increasing processor frequencies and pipeline depths are also reaching their limits.(6) Deeper pipelines increase the number of stalls from data dependencies and increase branch misprediction penalties.”