Power efficient processor architecture and the cell processor

By H. Peter Hofstee. International Symposium on High-Performance Computer Architecture, 2005

393 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/0b0dfd11b4366be930e1b15f149f86ce776b5465

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In Computer Networks and Communications

In Electrical and Electronic Engineering

Citations in the corpus

Horton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing (2016, methodology): “In the case where neither has spare slots, BCHTs resort to cuckoo hashing, a technique that resolves collisions by evicting and rehashing elements when too many elements vie for the same bucket.”
The worst-case execution-time problem—overview of methods and survey of tools (2008, methodology): “Outside the mobile phone industry, the IBM Sony-Toshiba Cell processor is a high-pro.le design using a simple in-order PowerPC core along with eight synergistic processing elements (SPEs) [Hofstee 2005].”
Introduction to the Cell multiprocessor (2005, background): “The challenge is therefore to find means to improve power efficiency along with performance [8].”
Cell Multiprocessor Communication Network: Built for Speed (2006, background): “The Cell processor addresses these issues by attempting to minimize pipeline depth, increase memory bandwidth, allow more simultaneous, in-flight memory transactions, and improve power efficiency and performance.(7) These design goals led to the use of flexible yet simple cores that use area and pow”
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs (2006, background): “…and Pipeline Parallelism in Stream Programs Michael I. Gordon, William Thies, and Saman Amarasinghe Massachusetts Institute of Technology Computer Science and Arti.cial Intelligence Laboratory {mgordon, thies, saman}@mit.edu Abstract As multicore architectures enter the mainstream, there is a…”