Cell Multiprocessor Communication Network: Built for Speed

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Dissecting the Graphcore IPU Architecture via Microbenchmarking (2019, methodology): “To study the IPU’s on-chip and off-chip interconnect performance, we adopt the terms, the methods and the interests of classic research focusing on the characterization of parallel systems and high-performance networks [3, 4, 5, 6].”
The multikernel: a new OS architecture for scalable multicore systems (2009, background): “Future hardware will comprise fewer chips but exhibit network effects inside the chip, such as with ring [38, 61] and mesh networks [68, 70].”
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (2008, background): “The realization of a scalable on-chip communication infrastructure faces critical challenges in meeting the large bandwidth capacities and stringent latency requirements demanded by CMPs in a power-efficient fashion [7], [8].”
Multiprocessor System-on-Chip (MPSoC) Technology (2008, background): “The Cell processor [13] has a PowerPC host and a set of eight processing elements known as synergistic processing elements.”
On the Design of a Photonic Network-on-Chip (2007, methodology): “A good example is represented by the IBM/Toshiba/Sony Cell Broadband Engine processor where the bulk of the interconnection network traffic is made of DMA transactions [18].”
High performance combinatorial algorithm design on the Cell Broadband Engine processor (2007, background): “We refer the reader to [21,10,18] for additional details.”