Introduction to the Cell multiprocessor

By J. Kahle, M. N. Day, H. Peter Hofstee, C. Johns, T. R. Maeurer, D. Shippy. 2005

1,082 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

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Citations in the corpus

Maximum-Likelihood Estimation With a Contracting-Grid Search Algorithm (2010, methodology): “The Sony PLAYSTATION 3 (PS 3) console includes the Cell/BE processor, a powerful yet inexpensive processing unit that has been widely applied for scientific computation [19]–[26].”
Artificial neural networks in hardware: A survey of two decades of progress (2010, positive): “IBM cell processor [264] with nine processor cores or its recent variant QS22 PowerXCell 8i [265] with their powerful vector processing capabilities hold good promise for highly parallel large scale ANN implementations or their fast emulations for comparative analysis.”
Rodinia: A benchmark suite for heterogeneous computing (2009, background): “…fast development of multicore/manycore CPUs, power limits, and increasing popularity of various accelerators (e.g., GPUs, FPGAs, and the STI Cell [16]), the performance of applications on future architectures is expected to require taking advantage of multithreading, large number of cores, and…”
Cell Multiprocessor Communication Network: Built for Speed (2006, methodology): “These models include the function-offload, device-extension, computational-acceleration, streaming, shared-memory-multiprocessor, and asymmetric-thread-runtime models.(8)”
Amdahl's Law in the Multicore Era (2008, background): “An alternative to a symmetric multicore chip is an asymmetric (or heterogeneous) multicore chip where one or more cores are more powerful than the others [3, 8, 9, 10, 14].”
High performance combinatorial algorithm design on the Cell Broadband Engine processor (2007, neutral): “) [17] is a novel architectural design by Sony, Toshiba, and IBM (STI), primarily targeting high performance multimedia and gaming applications.”
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (2008, background): “At the chip scale, the trend toward multicore architectures and chip multiprocessors (CMPs) for driving performance-per-watt by increasing the number of parallel computational cores is dominating new commercial releases [2], [3], [4], [5], [6].”
Express virtual channels: towards the ideal interconnection fabric (2007, background): “…Princeton, NJ 08544 Microprocessor Technology Labs, Intel Corp., Santa Clara, CA 95052 {amitk, peh, jha}@princeton.edu, partha.kundu@intel.com ABSTRACT Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip…”
Quantum Chemistry on Graphical Processing Units. 1. Strategies for Two-Electron Integral Evaluation. (2008, background): “Since 16 is not a multiple of 36, some blocks like block (4, 1 ) calculate primitive integrals which belong to different contracted integrals like (11|12) and (11|13).”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, methodology): “In order to predict the chip area, we investigate some die photos, such as Cell Processor [16], Sun UltraSPARC T1 [19], etc. and estimate the area of an 8-core CMP without caches to be 60 mm 2 .”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, background): “In particular, our experiments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration.”
Accelerating Compute-Intensive Applications with GPUs and FPGAs (2008, background): “GPUs and FPGAs, together with other accelerators such the vector processors of IBM’s Cell [11], DSPs (digital signal processors), media processors and network processors, can process work offloaded by the CPU and send the results back upon completion.”