DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs

By Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-mei W. Hwu, Deming Chen. 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018

361 citations recorded by the source corpus.

Building a high-performance FPGA accelerator for Deep Neural Networks (DNNs) often requires RTL programming, hardware verification, and precise resource allocation, all of which can be time-consuming and challenging to perform even for seasoned FPGA developers. To bridge the gap between fast DNN construction in software (e.g., Caffe, TensorFlow) and slow hardware implementation, we propose DNNBuilder for building high-performance DNN hardware accelerators on FPGAs automatically. Novel techniques are developed to meet the throughput and latency requirements for both cloud- and edge-devices. A number of novel techniques including high-quality RTL neural network components, a fine-grained layer-based pipeline architecture, and a column-based cache scheme are developed to boost throughput, reduce latency, and save FPGA on-chip memory. To address the limited resource challenge, we design an automatic design space exploration tool to generate optimized parallelism guidelines by considering external memory access bandwidth, data reuse behaviors, FPGA resource availability, and DNN complexity. DNNBuilder is demonstrated on four DNNs (Alexnet, ZF, VGG16, and YOLO) on two FPGAs (XC7Z045 and KU115) corresponding to the edge- and cloud-computing, respectively. The fine-grained layer-based pipeline architecture and the column-based cache scheme contribute to 7.7x and 43x reduction of the latency and BRAM utilization compared to conventional designs. We achieve the best performance (up to 5.15x faster) and efficiency (up to 5.88x more efficient) compared to published FPGA-based classification-oriented DNN accelerators for both edge and cloud computing cases. We reach 4218 GOPS for running object detection DNN which is the highest throughput reported to the best of our knowledge. DNNBuilder can provide millisecond-scale real-time performance for processing HD video input and deliver higher efficiency (up to 4.35x) than the GPU-based solutions.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/a821a00c54749a69a9d9fe0a7411de590d247715

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Citations in the corpus

Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search (2019, methodology): “In consequence, it is common to apply tiling technique to split convolutional operations into multiple small tasks [8, 12, 13, 15].”
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “Frameworks such as DNNWeaver [414], DNNBuilder [415], T2S-Tensor [416], and HeteroCL [417] have been developed recently for FPGA, ASIC, and other DL hardware accelerators for efﬁcient EI.”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, background): “…PUMA [153], FPSA [154] Toolset/Framework Data Parallelism [106], OWT [107], NEUTRAMS [100], Perform-ML [101], Adaptive-Classiﬁer [102], DNNBuilder [103], Group Scissor [104], FFT-CNN [105], HyPar [108], NNest [155] Table 2: Landscape of DNN accelerators ( accelerators highlighted in cyan are…”
Hardware/Software Co-Exploration of Neural Architectures (2019, neutral): “In the early stage, research efforts are mainly focusing on designing accelerators on a single FPGA [29], [30], [31], [32].”
Advances, challenges and opportunities in creating data for trustworthy AI (2022, methodology): “…, AI model building is becoming increasingly turn-key with technologies such as automated machine learning (AutoML), which automates model design and hyperparameter tuning, large public repositories of trained models, and industry-standard platforms such as PyTorch, Tensorflow and so on 4–6 .”