Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs

By Xuechao Wei, Cody Hao Yu, P. Zhang, Youxiang Chen, Yuxin Wang, Hangtao Hu, Yun Liang, Jason Cong. Design Automation Conference, 2017

421 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b02b8096567addbe78ab3e39d8dd8f105d428eb0

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In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

In Hardware and Architecture

Citations in the corpus

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “Systolic Array Architecture for CNN [195].”
SPINN: synergistic progressive inference of neural networks over device and cloud (2020, methodology): “To optimise the execution of CNN workloads, several solutions have been proposed, from compiler [1, 30, 65] and runtime optimisations [36, 43, 49] to custom cloud [7, 19, 34] and accelerator designs [75, 79].”
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs (2018, background): “Most of the works mentioned above and others [33–35], target inefficient ConvNets on middle to high-end FPGA devices.”
Edge Computing for Autonomous Driving: Opportunities and Challenges (2019, neutral): “[47] X.”
DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs (2018, background): “The authors in [9] design a framework with systolic arrays to speedup DNN inference.”
Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, background): “While there has been significant prior work on scheduling a single DNN model efficiently over one (or more distributed) accelerators [65, 95, 100, 102, 115, 122], scheduling multiple models simultaneously is relatively unexplored, and is the focus of this work.”
The Deep Learning Compiler: A Comprehensive Survey (2020, methodology): “y determined by the design space exploration using various strategies, such as combining the performance model and auto-tuning. DNN Weaver [83], Angel-Eye [44], ALAMO [67], FP-DNN [43], SysArrayAccel [101] are typical FPGA DL compilers targeting the processor architecture. What’s more, the PUs and P”
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs (2020, methodology): “Wei et al. [50] implemented CNN on an FPGA using a systolic array architecture, which can achieve high clock frequency under high resource utilization.”
Hardware implementation of memristor-based artificial neural networks (2024, positive): “Another option is to use ﬁ eld programable gate arrays (FPGAs), which consume much less energy than GPUs while providing an intermediate computing ef ﬁ ciency between CPUs and GPUs 13 – 17 .”
FINN-R (2018, methodology): “[61] as well as recent Xilinx demonstration at SC’2017, clearly show close to possible peak performance for higher precision implementations on AWSF1.”