DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

By Chao Wang, Lei Gong, Qi Yu, Xi Li, Yuan Xie, Xuehai Zhou. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016

320 citations recorded by the source corpus.

As the emerging field of machine learning, deep learning shows excellent ability in solving complex learning problems. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses significant challenge to construct a high performance implementations of deep learning neural networks. In order to improve the performance as well as to maintain the low power cost, in this paper we design deep learning accelerator unit (DLAU), which is a scalable accelerator architecture for large-scale deep learning networks using field-programmable gate array (FPGA) as the hardware prototype. The DLAU accelerator employs three pipelined processing units to improve the throughput and utilizes tile techniques to explore locality for deep learning applications. Experimental results on the state-of-the-art Xilinx FPGA board demonstrate that the DLAU accelerator is able to achieve up to $36.1 {\times }$ speedup comparing to the Intel Core2 processors, with the power consumption at 234 mW.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/431a1a620b762750ac92b35d97de67169eb8069c

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In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

Citations in the corpus

RILOD: near real-time incremental learning for object detection at the edge (2019, background): “ucing the computation cost on the mobile devices by compressing pre-trained deep learning models [10, 9, 20, 3], designing lightweight neural network architectures [16, 13], or hardware accelerations [15, 37] | these papers have not addressed the incremental learning problem in mobile vision. Deep I”
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, background): “There exists an abundance of architectures for CNN inference [65], [66], [67], [68], [69], [70], [71], [72], [73], [74], [75], [76], [77], [78], [79].”
A Survey on Deep Learning (2018, background): “Wang et al. [162] use a Deep Learning Accelerator Unit (DLAU) as a scalable architecture that uses three pipelined processing units.”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “[197] proposed a scalable design on FPGA for accelerating deep learning algorithms.”
Edge Computing for Autonomous Driving: Opportunities and Challenges (2019, background): “We have seen much recent progress on acceleration localization and perception functions, with many studies focused on reconfigurable fabrics [44]–[48]; however, with limited chip area, it is inefficient to integrate one accelerator for each perception and localization task.”
A survey on deep learning for big data (2018, background): “FPGA-based approaches have also explored for large-scale deep learning models in recent years [69,70].”
Efficient Incremental Learning for Mobile Object Detection (2019, background): “…on reducing the computation cost on the mobile devices by compressing pre-trained deep learning models [10, 9, 20, 3], designing lightweight neural network architectures [16, 13], or hardware accelerations [15, 37] — these papers have not addressed the incremental learning problem in mobile vision.”