Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistors
By Jing Guo, Ali Javey, H. Dai, Mark S. Lundstrom. IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004
153 citations recorded by the source corpus.
Subfields: Materials Chemistry
View Paper: https://www.semanticscholar.org/paper/a5c9c2f4a93c95a88b923d2458dfbe14a8d9f29b
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Materials Chemistry
- Phaedon Avouris
- Joerg Appenzeller
- H. Philip Wong
- Jing Guo
- Joachim Knoch
- Zhihong Chen
- Aaron D. Franklin
- Yu-ming Lin
Citations in the corpus
- Performance Comparison of Graphene Nanoribbon FETs With Schottky Contacts and Doped Reservoirs (2008, methodology): “For what concerns the intrinsic switching time τ instead, which represents the typical figure of merit for digital applications, we have used a previously developed comparison method that takes into account the power supply, ON, and OFF states [28].”
- Assessment of high-frequency performance potential of carbon nanotube transistors (2005, background): “(The major effect of the 4-nm-thick native oxide is to decrease the parasitic capacitance between the gate and the source (drain) electrode by a factor of 2, which does not change the qualitative conclusions of the paper.) The threshold voltage of the transistor was treated as a fitting parameter, w”
- Nanowire Transistor Performance Limits and Applications (2008, methodology): “In order to make a fair comparison with planar devices, the NWFET performance metrics were defined following the benchmarking method proposed by Intel [82], [83].”
- Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design (2005, methodology): “By performing the type of analysis described above for both, the T-CNFET and the C-CNFET, we are able to evaluate the gate delay τ as a function of Vdd at a fixed Ion/Ioff ratio of 1000 [39].”
- Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs (2008, background): “5 with a constant VDDbias window as explained in [38].”
- Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits (2009, background): “CARBON Nanotube Field Effect Transistors (CNFETs) are promising candidates as extensions to silicon CMOS due to excellent intrinsic delay (CV/I) at the device level [1]–[4].”
- A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements (2015, methodology): “Nonequilibrium Green’s function (NEGF) formalism [16] has been extensively employed to simulate the quantum transport in CNTFETs and assess their performance [7], [8], [17].”