Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

By N. Lindert, L. Chang, Yang‐Kyu Choi, E. Anderson, Wen-Chin Lee, Tsu-Jae King, Jeffrey Bokor, Chenming Hu. IEEE Electron Device Letters, 2001

152 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/9f05c58970c9a3db6e63a3f54f5e5e00683f67f4

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In Electrical and Electronic Engineering

1. Mamidala Jagadesh Kumar
2. Anurag Chaudhry
3. Supriyo Datta
4. Mark S. Lundstrom
5. Eric Pop
6. Anisur Rahman
7. Siyu Koswatta
8. Ian F. Akyildiz

Citations in the corpus

• High performance fully-depleted tri-gate CMOS transistors (2003, background): “the patterning of the Fin, rather than the physical gate length patterning [ 4 ].”
• Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review (2004, unknown): “terning [76].”
• Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET (2004, background): “But, since the thickness of silicon between the two gates is smaller than the physical gate length, the most critical lithography step in printing the DG transistor becomes patterning of the thin-film, rather than the physical gate-length patterning [ 6 ].”