A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs

By Kinam Kim, Jooyoung Lee. IEEE Electron Device Letters, 2009

137 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7bc046671369ba23568ff03bbee6ba04a91bd092

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Onur Mutlu
2. Jamie Liu
3. Ben Jaiyen
4. Richard Michael Veras
5. Yoongu Kim

Citations in the corpus

• Memory scaling: A systems architecture perspective (2013, background): “However, only a small number of weak rows require a high refresh rate [31, 44] (e.”
• Data retention in MLC NAND flash memory: Characterization, optimization, and recovery (2015, unknown): “tics of modern DRAM devices [37][38][39] and proposed optimizations to”
• RAIDR: Retention-aware intelligent DRAM refresh (2012, methodology): “Retention time within each category follows a log-normal distribution [8, 21, 25].”