Gate length scaling and threshold voltage control of double-gate MOSFETs

By Leland Chang, Stephen Tang, Tsu-Jae King, J. Bokor, Chenming Calvin Hu. International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000

181 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/77f8de528971eba8a9adef5b8193a0f508ecf2e2

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In Electrical and Electronic Engineering

Citations in the corpus

A spacer patterning technology for nanoscale CMOS (2002, background): “For the FinFET, short-channel effects can be suppressed by employing a body thickness (silicon fin width) which is approximately half of gate length [3], [8].”
Sub-60-nm quasi-planar FinFETs fabricated using a simplified process (2001, background): “The Si Ge gate composition is chosen to provide the desired threshold voltage [3], [7].”
An adjustable work function technology using Mo gate for CMOS devices (2002, background): “In order to maintain good short-channel performance and proper threshold voltages, the gate work functions of the n-FETs and p-FETs must be close to those of nand p doped poly-Si for bulk-Si CMOS devices and within 0.2 eV of Si mid-gap in novel structures such as double-gate MOSFETs [3].”
Role of scattering in nanotransistors (2002, background): “The reason for this is the large on-current and better scaling properties it offers, when compared to bulk-type MOSFETs [11], [12], [13], [14], [15], [16].”
Nanoscale CMOS spacer FinFET for the terabit era (2002, background): “Short-channel effects are suppressed by employing a thin-body layer (Si-fin width) that is approximately half of gate length [2], [ 5 ].”