Thermal management of 3D IC integration with TSV (through silicon via)

By John H. Lau, T. Yue. Electronic Components and Technology Conference, 2009

177 citations recorded by the source corpus.

Subfields: Automotive Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/51d857261106d497fe7f1ceab4d030d26fe54291

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Automotive Engineering

1. Satish G. Kandlikar
2. John H. Lau

In Electrical and Electronic Engineering

1. Satish G. Kandlikar
2. John H. Lau
3. Akhilesh V. Bapat

Citations in the corpus

• Overview and outlook of through‐silicon via (TSV) and 3D integrations (2011, methodology): “Figure 14 shows the equivalent thermal conductivity of a TSV in the vertical direction (keq,z 1⁄4 150 þ 188D/P) and horizontal directions (keq,x 1⁄4 keq,y 1⁄4 150 þ 105D/P) (Lau and Tang, 2009).”
• TSV manufacturing yield and hidden costs for 3D IC integration (2010, background): “5x10/C) [6-8], (2) less Cu plating, (3) higher throughput, and (4) more space for routing.”
• Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits (2014, background): “Lau and Yue [35] analyzed the thermal performance of a microchannel cooled 3D IC stack with copper TSVs.”