Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs

By Sungjun Im, Kaustav Banerjee. International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000

229 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/638152e68d2fa226aa7971fa5bf8057e0116dfa5

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Kaustav Banerjee
2. Navin Srivastava
3. Shukri J. Souri
4. Krishna C. Saraswat
5. Pawan Kapur
6. Yan Zhang
7. Hong Li
8. Jian-Qiang Lu

Citations in the corpus

• A thermal-driven floorplanning algorithm for 3D ICs (2004, background): “The four side walls and top of the chip are treated as ambient, since the chip is usually packaged in thermally insulated materials.”
• 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration (2001, methodology): “D ICs is heat dissipation [49], [50].”
• Scaling analysis of multilevel interconnect temperatures for high-performance ICs (2005, background): “It is important to assess the correlation between thermal conductivity and dielectric constant in order to evaluate the tradeoff between electrical and thermal performance.”