Scaling analysis of multilevel interconnect temperatures for high-performance ICs

By Sungjun Im, Navin Srivastava, Kaustav Banerjee, Kenneth E. Goodson. IEEE Transactions on Electron Devices, 2005

190 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials

View Paper: https://www.semanticscholar.org/paper/fd32161c176b02442a3b6286891d7b41014219a0

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Hong Li
2. Kaustav Banerjee
3. Chuan Xu
4. Navin Srivastava
5. Wen-Yan Yin
6. Franz Kreupl
7. J. Mao
8. H. Philip Wong

In Electronic, Optical and Magnetic Materials

1. Kaustav Banerjee
2. Hong Li
3. Chuan Xu
4. Navin Srivastava

Citations in the corpus

• Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects (2008, background): “electromigration reliability concerns that plague nanoscale Cu interconnects [6]‐[ 8 ].”
• Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics (2010, background): “Increased wire resistivity leads to increased Joule heating and degraded electromigration lifetime, which result in decreased maximum allowed current density in copper wires [2]–[4].”
• On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects (2009, background): “For low via resistance values, self-heating in individual vias has a small impact on the overall temperature of the interconnect stack [15].”
• Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects (2009, background): “All of these unique properties indicate that CNT and GNR could be potentially employed as alternative materials for next-generation nanoscale interconnects, which can enhance the electrical performance as well as eliminate electromigration reliability concerns that plague nanoscale Cu interconnects ”
• Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods (2006, background): “…temperature Tmetal is given by Tmetal ¼ Tchip þ Tself Tself ¼REI2rmsR ;self (2) where Tself is the temperature rise of the metal interconnect due to the flow of current, RE is the electrical resistance of interconnect, and R ;self is the thermal impedance of the interconnect line to the substrate.”