Characterization and Modeling of High-Switching-Speed Behavior of SiC Active Devices

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Modeling and Analysis of SiC MOSFET Switching Oscillations (2016, methodology): “study is carried out to investigate the effect of the parasitic elements in [22], similar to the empirical analysis in [17].”
Evaluation of switching performance of SiC devices in PWM inverter fed induction motor drives (2014, methodology): “Nowadays, the widely accepted method to assess the switching performance of power devices is the double pulse test (DPT) [9-11].”
Package Parasitic Inductance Extraction and Simulation Model Development for the High-Voltage Cascode GaN HEMT (2014, methodology): “The operation principle of the current shunt is elaborated in [21].”
Analytical loss model of high voltage GaN HEMT in cascode configuration (2014, background): “The most popular way to estimate the switching loss of high voltage devices is based on measurement [15][18].”
Development of a SiC JFET-Based Six-Pack Power Module for a Fully Integrated Inverter (2013, background): “It is demonstrated in [48] that JFET drain”
A 1200-V, 60-A SiC MOSFET Multichip Phase-Leg Module for High-Temperature, High-Frequency Applications (2014, background): “the standard double-pulse testing method [29].”
Instability in Half-Bridge Circuits Switched With Wide Band-Gap Transistors (2014, background): “[18], [19] provide an empirically based analysis of the parasitic elements that contribute to the pronounced natural ring-down in WBG applications.”