Cacti 3. 0: an integrated cache timing, power, and area model

By Premkishore Shivakumar, N. Jouppi. 2001

804 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/440d511b0a358b74d58cad41e5b089b273c5a5e2

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Citations in the corpus

Secure program execution via dynamic information flow tracking (2004, methodology): “The access latency for a larger cache is estimated using the CACTI tool [22].”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, methodology): “The CACTI tool was first released by Wilton and Jouppi in 1993 [43] and it has undergone four major revisions since then [31, 32, 35].”
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (2002, background): “0, which accounts for capacity, sub-bank organization, area, and process technology [27].”
Cooperative Caching for Chip Multiprocessors (2006, result): “These latencies are modeled similar to those in previous proposals [27,104,159], and consistent with CACTI [132] results.”
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction (2003, unknown): “CACTI 3.0: An integrated cache timing, power and area model.”
System level analysis of fast, per-core DVFS using on-chip switching regulators (2008, methodology): “We use SESC [25], a multi-core simulator, integrated with power-models based on Wattch [7], Cacti [29], and Orion [32].”
Temperature and supply Voltage aware performance and power modeling at microarchitecture level (2005, methodology): “0 toolset [31], then apply our formulas for power consumption to each SRAM array.”
A NUCA Substrate for Flexible CMP Cache Sharing (2007, methodology): “We estimated bank access latencies using Cacti [18] and a wire delay model [1].”