System level analysis of fast, per-core DVFS using on-chip switching regulators

By W. Kim, M. Gupta, Gu-Yeon Wei, David M. Brooks. 2008

787 citations recorded by the source corpus.

How researchers see this paper

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Chasing Carbon: The Elusive Environmental Footprint of Computing (2020, background): “In addition to architectural innovations, circuit designers have enabled high-performance and low-power hardware through efforts that include clock/power gating [115], DVFS [116], and circuit-level timing speculation [117].”
GPUWattch: enabling energy optimizations in GPGPUs (2013, result): “First, we assume a fast responding on-chip regulator that can make P-state transitions quickly within 500 cycles, which are similar to those used by Kim et al . in prior work for CPUs [19].”
Heracles: Improving resource efficiency at scale (2015, methodology): “For power isolation, Heracles uses CPU frequency monitoring, Running Average Power Limit (RAPL), and per-core DVFS (hardware features) [3, 37].”
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, background): “[16] describes designs of on-chip regulators.”
Thread motion: fine-grained power management for multi-core systems (2009, methodology): “Finally, fine-grained power management techniques using voltage dithering [5] and using on-chip regulators to obtain fast, percore DVFS [15] have been previously proposed.”